A Fully Differential SAR/Single-Slope ADC for CMOS Imager Sensor

This paper presents a fully differential two-step column- parallel successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). The ADC consists of a high 6-bit SAR ADC and a low 6-bit SS ADC. The differential sampling circuit eliminates the fixed offset of the sampling switch, reduces nonlinear errors, and improves the signal to noise ratio. This ADC is designed in UMC 0.11 mu m CMOS process. The ADC has the differential nonlinearity of -0.25/+0.25 LSB and the integral nonlinearity of -0.38/+0.56 LSB. The signal-to-noise and distortion ratio of the ADC is 73.0 dB and the spurious free dynamic range is 90.0 dB at the sampling rate of 227 kS/s when the input frequency is 11.0 kHz.