A Physics-Based Model of On-chip Decoupling Capacitor for Accurate Power Integrity Analysis

被引：0
|
作者：
Cheng, Yu-Jen [1 ]
Chuang, Hao-Hsiang [1 ]
Hsia, Chun [2 ]
Chen, Wen-Wei [2 ]
Huang, Wen-Po [2 ]
Wu, Tzong-Lin [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Commun Engn, Dept Elect Engn, Taipei 10617, Taiwan
[2] Etron Technol Inc, 6,Technol Rd 5,Hsinchu Sci Pk, Hsinchu 30078, Taiwan
来源：
2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) | 2011年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A physics-based equivalent circuit model of onchip decoupling capacitor for chip modelling is proposed for use in accurate power integrity (PI) analysis. The proposed model can be easily applied to on-chip decoupling capacitor design based on the construction flow. The accuracy of the model has been verified with circuit simulation. By using this model and an incomplete one, a case study of chip-package co-simulation in Hspice environment is investigated, which successfully demonstrate the purpose of the proposed model.
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页数：4
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