Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD (R) to deposit a TSV liner SiO2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO2. In addition, solid-solid inter-diffusion bonding of 3-mu m-thick Sn with 0.5-mu m-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190 degrees C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.