Comparative Analysis Of the HEVC Decoder on Two Embedded Processors using NEON Technology

被引：0
|
作者：
El Ansari, Abdessamad. [1 ]
Mansouri, Anass. [2 ]
Ahaitouf, Ali. [1 ]
机构：
[1] Univ Sidi Mohammed Ben Abdellah, LERSI Lab, FSTF, Fes, Morocco
[2] Univ Sidi Mohammed Ben Abdellah, LERSI Lab, ENSAF, Fes, Morocco
来源：
2016 IEEE/ACS 13TH INTERNATIONAL CONFERENCE OF COMPUTER SYSTEMS AND APPLICATIONS (AICCSA) | 2016年
关键词：
HEVC; decoder; NEON; and complexity; embedded processor; VIDEO CODING HEVC; IMPLEMENTATION; EFFICIENCY; STANDARD;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This work presents a comparison of two implementations of the last software version of The High Efficiency Video Coding (HEVC) decoder in a single low cost processor ARM Cortex-A series using NEON architecture which is a Single Input Multiple Data (SIMD). By using this technology of optimization, the whole execution time is reduced up to x4. We have analyzed separately all the blocks in the decoder and determined the consumed time percentage of each one compared to the whole time. This allows us to detect the more time consuming blocks. Then, we can find an optimal way to accelerate their functioning.
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页数：4
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