Distortionless space-time adaptive processor based on MVDR beamformer for GNSS receiver

被引:39
|
作者
Dai, Xinzhi [1 ]
Nie, Junwei [1 ]
Chen, Feiqiang [1 ]
Ou, Gang [1 ]
机构
[1] Natl Univ Def Technol, Coll Elect Sci & Engn, Deya St 109, Changsha, Hunan, Peoples R China
来源
IET RADAR SONAR AND NAVIGATION | 2017年 / 11卷 / 10期
关键词
satellite navigation; radio receivers; space-time adaptive processing; array signal processing; satellite tracking; correlation methods; interference suppression; filtering theory; distortionless space-time adaptive processor; MVDR beamformer; GNSS receiver; globe navigation satellite system receiver performance; harsh interference suppression; sustained interference suppression; STAP; cross-correlation function distortions; tracking performance; acquisition performance; high-accuracy GNSS applications; minimum variance disstortionless response beamformer; steering vector information; tapped delay line; space-time filter response linearity; carrier phase measurements; INTERFERENCE; ANTENNA; SATELLITE; MITIGATION; SIGNALS; ARRAY;
D O I
10.1049/iet-rsn.2017.0168
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The utilising of space-time adaptive processing (STAP) can effectively enhance the globe navigation satellite system (GNSS) receivers' performance in suppressing harsh, sustained interference. However, STAP may introduce significant biases and distortions on the cross-correlation functions, which would deteriorate acquisition and tracking performance. To achieve high-accuracy GNSS applications in challenging environments, these biases and distortions must be mitigated. A novel distortionless space-time adaptive processor based on minimum variance disstortionless response (MVDR) beamformer is proposed. By combining the information of steering vector and constraining the taps number of tapped delay line to be odd, the proposed processor can maintain the linearity of space-time filter response and it introduces no biases into the code and carrier phase measurements. The effectiveness of the proposed processor is demonstrated by theoretical analysis and simulations.
引用
收藏
页码:1488 / 1494
页数:7
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