Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders

被引：0

作者：

Strangio, S. ^{[1
,2
]}

Palestri, P. ^{[1
]}

Lanuzza, M. ^{[2
]}

Esseni, D. ^{[1
]}

Crupi, F. ^{[2
]}

Selmi, L. ^{[1
]}

机构：

[1] Univ Udine, DIEG, Via Sci 206, I-33100 Udine, Italy

[2] Univ Calabria, DIMES, Via P Bucci 42C, I-87036 Arcavacata Di Rende, CS, Italy

来源：

2016 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2016) | 2016年

关键词：

TFET; III-V compounds; VLSI; full adder;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a benchmark of a virtual III-V TFET nanowire technology platform against the predictive models of CMOS FinFETs for the 10-nm technology node. The standard 28T full adder and the 32-bits ripple carry adder are used as vehicle circuit/architecture for the comparison, respectively. Figures-ofmerit including delays, energy and energy-delay plots are discussed.

引用

页码：139 / 142

页数：4

共 2 条

[1] Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
Strangio, S.
Palestri, P.
Lanuzza, M.
Esseni, D.
Crupi, F.
Selmi, L.
SOLID-STATE ELECTRONICS, 2017, 128 : 37 - 42
[2] PDK development for 10nm III-V/Ge IFQW CMOS technology including statistical variability
Liao, Si-Yu
Towie, Ewan A.
Balaz, Daniel
Riddet, Craig
Cheng, Binjie
Asenov, Asen
2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), 2013, : 220 - 223

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