A CAD-based approach to failure diagnosis of CMOSLSI with single fault using abnormal I-DDQ

A CAD-based fault diagnosis technique for CMOS-LSI with single fault using abnormal IDDQ has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducing the faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal IDDQ. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal IDDQ exists in the inner logic state with normal IDDQ or not. The former block is regarded as normal block and the latter block is regarded as faulty block. The fault of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours and reliable extraction of the fault location.