DyAFNoC: Characterization and Analysis of a Dynamically Reconfigurable NoC using a DOR-based Deadlock-Free Routing Algorithm

被引:0
|
作者
Castillo, Ernesto Villegas [1 ]
Miorandi, Gabriele [1 ]
Chau, Wang Jiang [1 ]
机构
[1] Univ Sao Paulo, Sch Engn, Dept Elect Syst, Sao Paulo, Brazil
关键词
INTERCONNECTION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:190 / 191
页数:2
相关论文
共 12 条
  • [1] Dynamically Reconfigurable NoC using a Deadlock-Free Flexible Routing Algorithm with a Low Hardware Implementation Cost
    Castillo, Ernesto Villegas
    Chau, Wang Jiang
    Miorandi, Gabriele
    Bertozzi, Davide
    2015 IEEE 6TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2015,
  • [2] A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
    Jackson, Chris
    Hollis, Simon J.
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (02) : 139 - 151
  • [3] A NEW DEADLOCK-FREE FAULT-TOLERANT ROUTING ALGORITHM FOR NOC INTERCONNECTIONS
    Jovanovic, Slavisa
    Tanougast, Camel
    Weber, Serge
    Bobda, Christophe
    FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 326 - +
  • [4] Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming
    Liu, Shuang
    Radetzki, Martin
    2023 IEEE 16TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP, MCSOC, 2023, : 332 - 339
  • [5] A Reconfigurable and Deadlock-Free Routing Algorithm for 2D Mesh Network-on-Chip
    Shi, Zewen
    Yang, Yueming
    Zeng, Xiaoyang
    Yu, Zhiyi
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 2934 - 2937
  • [6] An Efficient Deadlock-Free Multicast Routing Algorithm for Mesh-Based Networks-on-Chip
    Lee, Kuen-Jong
    Chang, Chin-Yao
    Yang, Hung-Yang
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [7] An Efficient Deadlock-Free Multicast Routing Algorithm for Mesh-Based Networks-on-Chip
    Lee, Kuen-Jong
    Chang, Chin-Yao
    Yang, Hung-Yang
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [8] Deadlock-Free Routing Algorithm of 2D-Torus Network-on-Chip Based on FPGA
    Li Z.-N.
    Li J.-J.
    Wang J.
    Yang D.
    Dongbei Daxue Xuebao/Journal of Northeastern University, 2021, 42 (01): : 1 - 6
  • [9] A communication model based on an n-dimensional torus architecture using deadlock-free wormhole routing
    Hölzenspies, P
    Schepers, E
    Bach, W
    Jonker, M
    Sikkes, B
    Smit, G
    Havinga, P
    EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2003, : 166 - 172
  • [10] An efficient deadlock-free tree-based routing algorithm for irregular wormhole-routed networks based on the turn model
    Sun, YM
    Yang, CH
    Chung, YC
    Huang, TY
    2004 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, PROCEEDINGS, 2004, : 343 - 352