Fabrication of Bulk-Si FinFET using CMOS compatible process

被引：13
|
作者：
Zhou Huajie [1 ]
Song Yi [1 ]
Xu Qiuxia [1 ]
Li Yongliang [1 ]
Yin Huaxiang [1 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China
来源：
MICROELECTRONIC ENGINEERING | 2012年 / 94卷
关键词：
FinFET; Bulk; Multi-gate; ON-RESISTANCE; STRAINED-SI;
D O I：
10.1016/j.mee.2012.01.004
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new CMOS (Complementary Metal Oxide Semiconductor) compatible Bulk-Si FinFETs fabrication process has been proposed. Compared with conventional fabrication processes of SOI (Silicon On Insulator) and Bulk-Si FinFETs, this new approach is of low cost and simple. High performance CMOS Bulk-Si FinFETs, the fin isolated to Si substrate by oxide, have been fabricated using this new approach. With lower body doping concentration (1 x 15 cm(-3)), PMOS shows Io(n/)I(off) ratio of 10(4) and short channel behavior with a subthreshold swing (SS) of 280 mV/dec. a DIBL (Drain Induced Barrier Lowering) value of 258 mV/V. NMOS device, with the body doping concentration up to 1 x 17 cm(-3), shows an I-on/I-off ratio larger than 10(7) and SS = 86 mV/dec and DIBL = 28 mV/V. (C) 2012 Elsevier B.V. All rights reserved.
引用
收藏
页码：26 / 32
页数：7
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