A 20 Gb/s 1:4 DEMUX without inductors and low-power divide-by-2 circuit in 0.13 μm CMOS technology

被引：6

作者：

Kim, Byung-Guk ^{[1
]}

Kim, Lee-Sup ^{[1
]}

Byun, Sangjin ^{[2
]}

Yu, Hyun-Kyu ^{[2
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Taejon 305701, South Korea

[2] Elect & Telecommun Res Inst, Taejon 305350, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 02期

关键词：

CMOS; DEMUX; delay-locked loop (DLL); latch; static frequency divider; LOGIC;

D O I：

10.1109/JSSC.2007.914332

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mu m process consumes 210 mW from 1.2 V logic supply.

引用

页码：541 / 549

页数：9

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