Creation and verification of phase compliant SoC hard IP for the fabless COT designers

As the semiconductor industry has begun volume production of sub-wavelength geometries, technologies such as Optical Proximity Correction (OPC) and Phase-Shift Masks (PSM) have become main stream. One of these approaches, Alternating PSM (AltPSM), has been adopted by leading edge semiconductor companies to meet high-performance IC manufacturing requirements. As part of a complete production flow for these high-performance processes, it is required that System-on-Chip (SoC) Hard Intellectual Property (IP) cores be "phase compliant". Only through phase compliance, the fabless Customer Owned Tooling (COT) semiconductor market is enabled to leverage the benefits of AltPSM technology. Traditional design rules cannot be used alone to create and verify phase compliant designs. This paper proposes a new methodology to create and verify phase-compliant SoC IP. The methodology was implemented and verified on Virage Logic's Single Port SRAM compilers for UMC's 0.13-micron MPU, high-performance CMOS logic process based on 70-nm transistor gates, which are manufactured utilizing patented AltPSM technology from Numerical Technologies, Inc. Examples of certain areas of the layout before and after phase compliance are presented. The timing characterization data is also included to show that the performance (speed) of the memory layouts was enhanced by 20% over regular 0.13 micron process. The paper concludes with some general remarks on how this methodology will be impacted as we move to 65nm node.