A vertical successive - Approximation A/D converter architecture for high-speed applications

被引：0

作者：

Hamdy, N ^{[1
]}

Soliman, H ^{[1
]}

Eid, A ^{[1
]}

机构：

[1] AAST, Coll Engn & Technol, Alexandria, Egypt

来源：

1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/MWSCAS.1998.759550

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A non-iterative successive approximation quantization technique that provides high throughput rates at low decision cost/bit is described. The MSB's are obtained in a flash-like architecture operating according to a unidirectional successive approximation algorithm. The LSB's are then generated by recycling the built-in flash-type quantizer. Resolution is extendable at minimum speed loss through cascading similar stages operating with pipeline timing.

引用

页码：542 / 545

页数：4

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