Memory hierarchy for high-performance and energy-aware reconfigurable systems

Run-time reconfigurable resources present many of the features such as high performance, flexibility and reusability demanded by next generation embedded systems. In addition, many emerging reconfigurable architectures have been optimised for low power. However, carrying out run-time reconfigurations often involves a costly reconfiguration overhead both in execution time and in energy consumption. Only the execution-time overhead was dealt with in the previous work. Here, the approach is significantly extended in order to reduce the reconfiguration energy overhead as well. To this end, a configuration memory hierarchy is proposed, with a shared memory layer consisting of a module optimised for performance combined with a module optimised for energy-efficient accesses. For this hierarchy, the authors have developed a mapping algorithm that decides where to load each configuration in order to achieve significant energy savings without introducing any performance degradation.