Evaluation of SystemC modelling of reconfigurable embedded systems

被引：10
|
作者：
Rissa, T [1 ]
Donlin, A [1 ]
Luk, W [1 ]
机构：
[1] Univ London Imperial Coll Sci Technol & Med, Dept Comp, London SW7 2BZ, England
来源：
DESIGNERS' FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION | 2005年
关键词：
D O I：
10.1109/DATE.2005.143
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.
引用
收藏
页码：253 / 258
页数：6
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