Design and hardware implementation of digital channel selection processor for radio receiver

被引：2

作者：

Grati, K ^{[1
]}

Ghazel, A ^{[1
]}

Naviner, L ^{[1
]}

机构：

[1] Ecole Super Commun, CS2R Team, MEDIATRON Lab, Ariana, Tunisia

来源：

Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology | 2004年

关键词：

digital decimating filter; low-power design; FPGA implementation;

D O I：

10.1109/ISSPIT.2004.1433710

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for Radio receiver. For an homodyne wide-band RF receiver and Sigma-Delta modulator, two filtering cascade structures composed of 5 stages Comb filter, FIR half-bandfilter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

引用

页码：152 / 156

页数：5

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