SPICE MODEL OF DRAIN INDUCED BARRIER LOWERING IN SYMMETRIC JUNCTIONLESS DOUBLE GATE MOSFET

A SPICE model of Drain Induced Barrier Lowering (DIBL) has been proposed for a symmetric junctionless double gate (JLDG) MOSFET. For this purpose, the potential distribution in the channel is obtained using the Poisson equation, and the threshold voltage is determined by the third derivative (TD) method. The SPICE model of DIBL should be expressed as a function of silicon thickness t(si) as well as channel length L-g, oxide thickness t(ox), and SPICE parameter eta such as sigma(D)= A eta L(g)(-3)t(si)(2)t(ox) due to the effect of silicon thickness on carrier transport in a nanostructure JLDG MOSFET, even though it is only defined by channel length and oxide thickness in SPICE model of conventional MOSFET. As a result, it is found that the proportional constant A is 22.0 and the static feedback coefficient eta is reasonably between 0.2 and 0.9. The DIBLs obtained by using the threshold voltage model published in other papers show a good agreement with those of this model regardless of the channel length at 20 nm or more, but the DIBLs of the other models are different at the sub-20 nm channel lengths from one another due to approximations of each other. Also we show that the DIBL for JLDG MOSFET is smaller than junction-based double gate MOSFET.