共 27 条
- [1] Efficient Implementations of Multiple Bit Burst Error Correction for Memories 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 602 - 604
- [2] Enhanced Error Correction against Multiple-Bit-Upset Based on BCH Code for SRAM 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
- [3] Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2024, 40 (04): : 525 - 537
- [5] A novel two-dimensional error correction code for multiple bit upsets mitigation in memories Yuhang Xuebao/Journal of Astronautics, 2014, 35 (02): : 227 - 234
- [6] Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction 2019 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2019,
- [7] Multi-Bit-Upset Memory Using New Error Correction Code Methodology 2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,
- [10] Hardened by design techniques for implementing multiple-bit upset tolerant static memories 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2786 - 2789