On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)

It is realized that having a method/apparatus that accurately measures voltage noise is imperative for ATE and SLT testing to 1) reliably sign-off on production patterns; 2) effectively optimize low power settings of scan architecture; 3) screen for defects during ATE testing and apply structural patterns on SLT at desired Voltage/Frequency points; This requires optimized noise profiles and hence localized noise monitors for appropriate tuning. In addition, with NVIDIA's chips foraying into the automotive space, functional safety has gained utmost priority, and the noise profile during In-System Test (IST) helps catch reliability and aging-related defects in the field that show up after stress and degradation. This paper proposes an enhancement to the in-system Noise Measurement macro (NMEAS) to record voltage noise during the application of structural DFT patterns, such as in ATE and SLT testing, which was not possible in the conventional noise measurement methods. The introduced technique utilizes a continuous free-running fast clock that feeds functional frequency to NMEAS during test which allows it to measure the voltage noise of the chip during both shift and capture phases. Also, a novel enable generation logic and a counter are introduced that allow for more precise characterization of the measured voltage noise data.