A mathematical steady-state design model for fully-integrated boost and buck DC-DC converters

被引：1

作者：

Wens, Mike ^{[1
]}

Steyaert, Michiel ^{[1
]}

机构：

[1] Katholieke Univ Leuven, B-3001 Heverlee, Belgium

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2012年 / 70卷 / 03期

关键词：

DC-DC; Model; Step-down; Step-up; Integrated output filter;

D O I：

10.1007/s10470-011-9639-0

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This brief discusses a mathematical steady-state model for fully-integrated boost and buck DC-DC converters, which takes all the significant resistive and dynamic power losses into account. The model provides a reduced calculation time by a factor 30 compared to SPICE. A 2%, or less, deviation in comparison with SPICE is achieved. The validation of the model through the measurements of both a fully-integrated boost and buck converter is demonstrated, resulting in an accuracy for the efficiency of 3 and 4% respectively.

引用

页码：369 / 375

页数：7

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