An improved non-uniformity correction algorithm and its hardware implementation on FPGA

被引:16
|
作者
Rong Shenghui [1 ]
Zhou Huixin [1 ]
Wen Zhigang [2 ,3 ]
Qin Hanlin [1 ]
Qian Kun [1 ]
Cheng Kuanhong [1 ]
机构
[1] Xidian Univ, Sch Phys & Optoelect Engn, Xian, Shaanxi, Peoples R China
[2] Chinese Acad Sci, Xian Inst Opt & Precis Mech, Xian, Shaanxi, Peoples R China
[3] Chinese Acad Sci, Key Lab Spectral Imaging Technol, Xian, Shaanxi, Peoples R China
基金
中国国家自然科学基金;
关键词
Infrared focal plane array; Non-uniformity correction; Neural network; Guided filter; Motion detection; FPGA; FOCAL-PLANE ARRAYS; INFRARED IMAGE SEQUENCES; FILTER; PASS;
D O I
10.1016/j.infrared.2017.07.007
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The Non-uniformity of Infrared Focal Plane Arrays (IRFPA) severely degrades the infrared image quality. An effective non-uniformity correction (NUC) algorithm is necessary for an IRFPA imaging and application system. However traditional scene-based NUC algorithm suffers the image blurring and artificial ghosting. In addition, few effective hardware platforms have been proposed to implement corresponding NUC algorithms. Thus, this paper proposed an improved neural-network based NUC algorithm by the guided image filter and the projection-based motion detection algorithm. First, the guided image filter is utilized to achieve the accurate desired image to decrease the artificial ghosting. Then a projection based moving detection algorithm is utilized to determine whether the correction coefficients should be updated or not. In this way the problem of image blurring can be overcome. At last, an FPGA-based hardware design is introduced to realize the proposed NUC algorithm. A real and a simulated infrared image sequences are utilized to verify the performance of the proposed algorithm. Experimental results indicated that the proposed NUC algorithm can effectively eliminate the fix pattern noise with less image blurring and artificial ghosting. The proposed hardware design takes less logic elements in FPGA and spends less clock cycles to process one frame of image. (C) 2017 Published by Elsevier B.V.
引用
收藏
页码:410 / 420
页数:11
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