Real time FFT processor implementation

被引：8
|
作者：
Minallah, Mian Sijjad [1 ]
Raja, Gulistan [1 ]
机构：
[1] Univ Engn & Technol, Dept Elect Engn, Taxila, Pakistan
来源：
SECOND INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES 2006, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/ICET.2006.335959
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper describes the implementation of a 64 point FFT Processor in VHDL. The implemented architecture [1] is well suited for realtime spectrum analysis in instrumentation and measurement applications. It uses a single butterfly processor instead of a column of butterfly processors. The butterfly consists of one multiplier and two adders. The paper describes the VHDL implementation of various units of this processor.
引用
收藏
页码：192 / +
页数：2
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