LoCCo-Based Scan Chain Stitching for Low-Power DFT

Power dissipation during scan testing of a systemon- chip can be significantly higher than that during functional mode, causing reliability and yield concerns. This paper proposes a logic cluster controllability (LoCCo)-based scan chain stitching methodology to achieve low-power testing. The scan chain stitching is made power aware by placing flip-flops with higher test combination requirements at the beginning of scan chains, while flip-flops with lower test combination requirements are put toward the end of scan chains. The test combination requirements are estimated through a simple logic cluster and flip-flop controllability identification algorithm. This method helps in consolidating care bits toward the beginning of scan chains. Hence, a significantly lower shift-in transition is achieved in the test patterns. The results from ITC' 99 and industrial designs in 28FDSOI and 40-nm CMOS technologies show a total shift-in transition reduction of up to 23.1% and average shift power reduction of up to 21.6% using the proposed method. The use of LoCCo methodology posed a negligible routing congestion overhead in the layout compared to the conventional method. LoCCo is also used as a base to apply other vector reordering low-power methods and gain 3.5x reduced computation time with almost similar power reduction as achieved by Bonhomme et al. independently.