Energy and performance trade-offs between instruction reuse and trivial computations for embedded applications

Instruction reuse (IR) and trivial computation (TC) elimination are two architectural techniques that aim at eliminating redundant code to better exploit instruction-level parallelism. While they have been extensively studied in isolation, this paper is the first to compare their relative efficiency. This is done using applications from the embedded domain. This paper establishes the relationship between the two techniques by framing the arithmetic instructions detected by each of them. While TC can only eliminate instructions where one of the operands is zero or one, IR has potentially a wider scope as it can potentially eliminate any instruction given that it has been executed before with the same set of operand values. Despite the wider scope, we have found that IR and TC can eliminate about the same fraction of instructions even if an infinitely large instruction reuse buffer is assumed (IR and TC can eliminate 26% and 22% of the instructions, respectively). Another quite surprising finding is that the two techniques target quite different sets of instructions suggesting that they can provide almost additive gains if combined. In combination, they can eliminate 40% of the instructions they target. In terms of energy-efficiency, we finally find that if an instruction reuse buffer of 256 entries is used, it uses 1% more energy than a processor without UR and TC reduces the energy consumption by 5.6%.