Evaluation of delay fault testability of LUT functions for improved efficiency of FPGA testing

Testing delay faults in FPGAs differs significantly from testing delay faults in circuits whose combinational sections can be represented as gate networks. Based on delay fault testability conditions, formulated in a form suitable for analysis of LUT-based FPGAs, we develop an original method for the evaluation of delay fault testability of LUT functions It relies on an indicator called delay fault activation profile. The proposed method supports an analysis and comparison of different procedures for the enhancement of detectability of FPGA delay faults that rely on transformations of user-defined functions of LUTs in the combinational logic block tinder test, We demonstrate the effectiveness of our method by applying it to prove the efficiency and to optimize a specific procedure for the transformation of LUT functions which preserves the blocking capability and input-output transition pattern of orginal functions.