High-Speed Signal Termination Analysis Using A Co-Simulation Approach

被引：0

作者：

Chang, Weng-Yew Richard ^{[1
]}

See, Kye-Yak ^{[1
]}

Soh, Wei-Shan ^{[2
]}

Oswal, Manish ^{[2
]}

Wang, Lin-Biao

机构：

[1] Guided Syst Div, DSO Natl Labs, 20 Sci Pk Dr, Singapore 118230, Singapore

[2] Nanyang Technol Univ, Div Circuits & Syst, Sch EEE, Singapore, Singapore

来源：

PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009) | 2009年

关键词：

termination; signal integrity; high-speed clock; EM transient co-simulation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Matched terminations of high-speed digital buses have long been the focus of high-speed board design. With increasing edge rates, proper bus termination has become even more crucial in today's high-speed PCB interconnect design. Using a co-simulation approach, the 3D electromagnetic (EM) effects of high-speed interconnects and the circuit behavioral IBIS models of active devices are combined to investigate highspeed clock termination designs. Such an approach allows the high-frequency effects to be taken into account and therefore yields good accuracy for realistic high-speed board. A practical example is demonstrated based on the co-simulation approach.

引用

页码：619 / +

页数：2

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