Design and Implementation a Hierarchical Co-Verification Platform for Gigabit Ethernet Controller of Multi-core Processor

被引:0
|
作者
Luo, Li [1 ]
He, Hongjun [1 ]
Ou, Guodong [1 ]
Pan, Guoteng [1 ]
机构
[1] Natl Univ Def Technol, Sch Comp Sci, Changsha, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
gigabit ethernet controller; co-verification platform; multi-core processor;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With growing interconnection network technology, Ethernet MAC (Media Access Control) controller integrated in processor chip for their network services has become the trend, This paper studies the design and pre-silicon verification of multi-core processor' Ethernet controller, how to improve the verification efficiency? Test bench validity and completeness is the great challenge of verification work. This paper puts forward the method to generate hierarchical classification and management respectively on verification resources and test bench, proposes a hierarchical software and hardware co-verification platform to verify functionality and preliminary performance evaluation, which improves the efficiency of verification, and accelerates the verification cycle of the target chip, the chip is tape out now.
引用
收藏
页码:1509 / 1513
页数:5
相关论文
共 50 条
  • [1] Design and implementation of FPGA verification platform for multi-core processor
    Chen, C. (hmioycc@gmail.com), 1600, Science Press (51):
  • [2] Hierarchical Memory System Design for a Heterogeneous Multi-core Processor
    Guo, Jianjun
    Lai, Mingche
    Pang, Zhengyuan
    Huang, Libo
    Chen, Fangyuan
    Dai, Kui
    Wang, Zhiying
    APPLIED COMPUTING 2008, VOLS 1-3, 2008, : 1504 - 1508
  • [3] A Design of the Trusted Platform Module Based on Multi-Core Processor
    Wang Yubo
    Mao Junjie
    2011 INTERNATIONAL CONFERENCE ON FUTURE COMPUTER SCIENCE AND APPLICATION (FCSA 2011), VOL 3, 2011, : 538 - 541
  • [4] Design and FPGA Implementation of Ten Gigabit Ethernet MAC Controller
    Yi, Qingming
    Shi, Min
    Zhong, Guisen
    2017 IEEE 2ND ADVANCED INFORMATION TECHNOLOGY, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (IAEAC), 2017, : 1395 - 1398
  • [5] FPGA Verification for Heterogeneous Multi-Core Processor
    Li X.
    Tang Z.
    Li W.
    Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2021, 58 (12): : 2684 - 2695
  • [6] Power Channel Design and Verification for Automotive Chipset with Multi-Core Processor
    Chen, Nansen
    2019 IEEE CPMT SYMPOSIUM JAPAN (ICSJ), 2019, : 227 - 232
  • [7] A Turbo Decoder Implementation for LTE Downlink Mapped on a Multi-Core Processor Platform
    Zhang, Qing
    Yu, Xueqiu
    Yu, Zhiyi
    Zeng, Xiaoyang
    2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [8] Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform
    Fan, Wenhua
    Chen, Chen
    Chen, Yun
    Yu, Zhiyi
    Zeng, Xiaoyang
    IEICE TRANSACTIONS ON COMMUNICATIONS, 2012, E95B (04) : 1241 - 1248
  • [9] Design and Implementation of Scalable, Transparent Threads for Multi-Core Media Processor
    Kodaka, Takeshi
    Sasaki, Shunsuke
    Tokuyoshi, Takahiro
    Ohyama, Ryuichiro
    Nonogaki, Nobuhiro
    Kitayama, Koji
    Mori, Tatsuya
    Ueda, Yasuyuki
    Arakida, Hideho
    Okuda, Yuji
    Kizu, Toshiki
    Tsuboi, Yoshiro
    Matsumoto, Nobu
    DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 1035 - 1039
  • [10] Hardware/software co-verification platform for EOS design
    Wang, P
    Liu, JS
    Zeng, LG
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 195 - 198