Efficient Delay-Matching Bus Routing by using Multi-layers

Recently, signal propagation delay in a circuit implemented in VLSI or PCB becomes a very important problem due to the increasing clock frequency, where signal delay should be adjusted to meet the requirement of the delay time. The delay can be roughly estimated by the net length. While, due to the circuit complexity and the high density of integration, a single layer routing may not be enough for delay estimation. In current research, there's an algorithm for length matching bus routing for signal delay which has high efficiency. However, it doesn't put the high density of integration into consideration. The purpose of this paper is to route several nets by using multiple layers on a high density board to meet the signal delay requirement, even if there exist obstacles in the routing area. Previous research put focus on the single layer routing without considering the complexity and density of the board. In this paper, the complexity and density are taken into account. In our proposed algorithm, the routing area is divided into subareas to solve the problem efficiently, and nets can be assigned to the proper layers to avoid obstacles. After the net assignment, path generation is executed. Then, some optimizations are made to meet the signal delay for each net. Finally, the routing paths of nets which satisfy the delay constraint are determined. Experimental results using several examples show that our proposed method is highly effective and efficient.