Area Efficient Test Circuit For Library Standard Cell Qualification

被引：0

作者：

Al-Frajat, Jaafar K. ^{[1
,3
]}

Flayyih, Wameedh Nazar ^{[4
]}

Sidek, Roslina Binti Mohd ^{[2
,3
]}

Samsudin, Khairulmizam ^{[1
]}

Rokhani, Fakhrul Zaman ^{[1
,3
]}

机构：

[1] Univ Putra Malaysia, Fac Engn, Dept Comp & Commun Syst Engn, Serdang, Malaysia

[2] Univ Putra Malaysia, Fac Engn, Dept Elect & Elect Syst Engn, Serdang, Malaysia

[3] Univ Putra Malaysia, Fac Engn, Smart Syst & Syst Chip S3oC, Serdang, Malaysia

[4] Univ Baghdad, Fac Engn, Dept Comp Engn, Baghdad, Iraq

来源：

2015 5TH INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS & APPLICATIONS (ICEAC) | 2015年

关键词：

Standard cell qualification; library validation; delay chain; TEG circuit; on-silicon measurement;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction.

引用

页数：4

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