Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V

With an ever-increasing usage of electronic controllers in various disciplines that could be attributed to Industry 4.0, Internet of Things (IoT) and quick shift in computational paradigms, a demand for high code density and faster controllers are expected at the diversified nodes that improve energy efficiency without performance penalty. RISC-V is an opensource Instruction Set Architecture (ISA) which is designed with modularized extensions, that enables to design processors with a provision of individual extension evaluation helping in the design of low-power and secure embedded controllers. Bit manipulation is one of the key operations performed in domains such as Cryptography, Communication and Networking protocols, Digital Signal Processing, Bioinformatics etc., which are currently implemented using RISC-V standard instruction set. This paper implements the 'B' extension of RISC-V that hosts instructions specific to operate at bit-level manipulations, which is absent in ratified unprivileged ISA manual. A quantitative analysis is performed to assess the impact of Bit Manipulative Instructions (BMI) in size and speed improvements using the EmbenchT benchmarks against the standard instruction set `IMAC' under the RV32 configuration. The results show significant improvements, with some programs achieving a speedup of 28% and size reduction of 20%.