Generic Self Repair Architecture with On-line Fault Diagnosis

被引：1

作者：

Kristofik, Stefan ^{[1
]}

Balaz, Marcel ^{[1
]}

Fischerova, Maria ^{[1
]}

机构：

[1] Slovak Acad Sci, Inst Informat, Bratislava, Slovakia

来源：

2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015) | 2015年

关键词：

Built-in self-repair; on-line testing; reconfigurable logic; logic core; system-on-chip; reliability;

D O I：

10.1109/DDECS.2015.58

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ever smaller nanotechnologies introduce new types of defects and fault mechanisms with negative influence on system on-chips (SoCs) reliability and operational life. This paper presents a fault diagnosis and repair procedure which is implemented into generic built-in self-repair architecture. The procedure utilizes on-line fault detection whereas repair is performed during off-line mode. Experimental results show quicker repair process and area overhead which is well below the additional area of triple modular redundancy system.

引用

页码：279 / 282

页数：4

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