How faults can be simulated in self-testable VLSI digital circuits?

Computer-made simulation of self-testable VLSI digital circuits is lime consuming process. This is why new methods are still being developed to optimise the simulation process and to reduce its duration The paper presents a new method of fault simulating, intended for self-testable digital circuits. In this method fault masking performed by in-circuit tester is estimated opt a base of only the signature itself, which is stored in compressor. Irt is not necessary to carry out time-consuming analysis of digital circuit's responses and comparing them with stoped model responses. On a base of performed simulations the observation was made that the developed method brings a substantial reducing of the duration of fault simulation processes performed for self-testable digital circuits. If means the research laboratory needs considerably less rime to verify; the carried out projects of digital circuits.