A Survey on Hardware Security Techniques Targeting Low-Power SoC Designs

被引：0

作者：

Ehret, Alan ^{[1
]}

Gettings, Karen ^{[2
]}

Jordan, Bruce R., Jr. ^{[2
]}

Kinsy, Michel A. ^{[1
]}

机构：

[1] Boston Univ, Dept Elect & Comp Engn, Adapt & Secure Comp Syst ASCS Lab, Boston, MA 02215 USA

[2] MIT, Lincoln Lab Lexingon, Cambridge, MA 02139 USA

来源：

2019 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC) | 2019年

关键词：

Hardware Security; System-on-Chip; Secure Enclave; PUF; Network-on-chip; Oblivious RAM; ATTACKS;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work, we survey hardware-based security techniques applicable to low-power system-on-chip designs. Techniques related to a system's processing elements, volatile main memory and caches, non-volatile memory and on-chip interconnects are examined. Threat models for each subsystem and technique are considered. Performance overheads and other trade-offs for each technique are discussed. Defenses with similar threat models are compared.

引用

页数：8

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