Low phase noise and Fast locking PLL Frequency Synthesizer for a 915MHz ISM Band

in this paper, Low phase noise and Fast locking PLL Frequency Synthesizer in a 0.18-um CMOS process is presented. This thesis application is the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer designs based upon self-biased techniques are presented. The PLL frequency synthesizer designs achieve process technology independence, fixed damping factor fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly. A fully-integrated, 915MHz band wireless transponder using CPFSK communication, frequency synthesizer in the frequency range of 320M similar to 960MHz with frequency resolution of 10MHz is designed in 0.18 mu m CMOS process and silicon performance is measured. Integer-N architecture is chosen for implementation. it consumes 20mW of power at 1.8V supply and core area is 540 mu m x 450 mu m. The measured phase-noises are -117.92dBc/Hz at 10MHz offset, respectively, with low settling time less than 3.3 mu s.