Hardware Attack Risk Assessment

被引：0

作者：

Moein, Samer ^{[1
]}

Gebali, Fayez ^{[1
]}

Gulliver, T. Aaron ^{[1
]}

El-Kharashi, M. Watheq ^{[2
]}

机构：

[1] Univ Victoria, Dept Elect & Comp Engn, Victoria, BC V8W 2Y2, Canada

[2] Ain Shams Univ, Comp & Syst Engn Dept, Cairo 11517, Egypt

来源：

2015 TENTH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS (ICCES) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Modern VLSI chips have high complexity and usually contain cryptographic processors to protect their data and external communications. Attackers target the hardware to imitate or understand the system design, gain access to the system or obtain encryption keys. They may also want to initiate attacks such as denial of service to disable the services supported by a chip, or reduce system reliability. In this paper, risk levels are defined for hardware attacks based on the accessibility, resources, and time required to successfully attack a system.

引用

页码：346 / 350

页数：5

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