A methodology to investigate UWB digital receiver sensitivity to clock jitter

Some UWB receivers, digitally oriented, sample the RF signal at a very high frequency close to 20 GHz. In that case, the phase noise and jitter performances of the clock synthesizer which controls the sampling process are crucial. This paper proposes a methodology to investigate UWB receiver sensitivity to clock jitter. First we develop jitter models in Delay Locked Loop (DLL) and Phase Locked Loop (PLL) synthesizers. These models are injected in a UWB chain in order to evaluate the sensitivity of sampling and correlation. Finally, some analytical expressions, fitting with the simulation results, are established.