A very-high-frequency CMOS four-quadrant analogue multiplier

被引：0
|
作者：
Li, SC
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new CMOS four-quadrant analogue multiplier which consists of three high speed unity-gain buffers and two NMOS transistors operated in the triode region is presented. Simulation results based on TSMC 0.6 mu m SPDM process parameters indicate for supply voltages of +/-2.5V. the linearity error can be kept below 5% for a differential input voltage range up to +/-1V. Total harmonic distortion at 10MHz with a 1V (peak) input signal at either input terminal with a +/-1V DC voltage at the other terminal is less than 5%. The simulated -3dB bandwidth of this multiplier is about 230MHz.
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页码：233 / 236
页数：4
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