A 40Gb/s 27mW 3-tap Closed-loop Decision Feedback Equalizer in 65nm CMOS

被引：0

作者：

Cao, Weidong ^{[1
]}

Wang, Ziqiang ^{[1
]}

Li, Dongmei ^{[1
]}

Zheng, Xuqiang ^{[1
]}

Huang, Ke ^{[1
]}

Yuan, Shuai ^{[1
]}

Li, Fule ^{[1
]}

Wang, Zhihua ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Tsinghua Natl Lab Informat Sci & Technol, Beijing, Peoples R China

来源：

2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2015年

关键词：

3-tap DFE; closed-loop; dynamic latch; clock-control summers array; energy efficiency; RECEIVER;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap differential pairs within clock-control summers array (CCSA) to accomplish the 2nd and 3rd tap stages design. The total power consumption of the 3-tap DFE is 27mW under 1V, achieving 0.67 pJ/bit energy efficiency.

引用

页数：4

共 45 条

[1] A 40Gb/s 39mW 3-tap Adaptive Closed-loop Decision Feedback Equalizer in 65nm CMOS
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Li, Fule
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[2] A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer in 65nm CMOS
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[3] Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (12) : 3243 - 3257
[4] A 3.75Gbps Configurable Continuous Time Linear Equalizer and 3-tap Decision Feedback Equalizer in 65nm CMOS
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[7] A 4mW 3-tap 10 Gb/s Decision Feedback Equalizer
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[8] A 27-Gb/s, 0.41-mW/Gb/s 1-Tap Predictive Decision Feedback Equalizer in 40-nm Low-Power CMOS
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[10] A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology
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IEICE ELECTRONICS EXPRESS, 2023, 20 (03):

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