A novel low power BPSK demodulator

被引：3

作者：

Luo, Zhenying ^{[1
]}

Sonkusale, Sameer ^{[1
]}

机构：

[1] Tufts Univ, Dept Elect & Comp Engn, Medford, MA 02155 USA

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.377880

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A novel low power Binary Phase Shift Keying (BPSK) demodulator architecture is presented. The design employs a Phase Frequency Detector (PFD) based Phase Locked Loop (PLL), which allows for low power consumption and a higher tracking and locking range compared to prior art. Using the proposed architecture, a 13.5 MHz BPSK demodulator has been designed and fabricated in a 0.5um CMOS technology. Simulation and chip measurement result show that this BPSK demodulator provides low power operation and robust performance.

引用

页码：3856 / 3859

页数：4

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