Ultrathin nitride/oxide (N/O) gate dielectrics for p+-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD thermal oxidation process

被引：52
|
作者：
Wu, YD [1 ]
Lucovsky, G
机构：
[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA
[2] N Carolina State Univ, Dept Phys, Raleigh, NC 27695 USA
来源：
IEEE ELECTRON DEVICE LETTERS | 1998年 / 19卷 / 10期
基金：
美国国家科学基金会;
关键词：
boron penetration; gate dielectrics; nitride; N/O;
D O I：
10.1109/55.720188
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Ultrathin nitride-oxide (N/Q similar to 1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFET's with boron-implanted polysilicon gates. Bored penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFET's with oxide dielectrics. In addition, improved interface characteristics. and hot carrier degradation immunity are also demonstrated for the devices,vith the N/O dual layer gate dielectrics.
引用
收藏
页码：367 / 369
页数：3
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