Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes

被引：0

作者：

Lorente, Vicente ^{[1
]}

Valero, Alejandro ^{[1
]}

Sahuquillo, Julio ^{[1
]}

Petit, Salvador ^{[1
]}

Canal, Ramon ^{[2
]}

Lopez, Pedro ^{[1
]}

Duato, Jose ^{[1
]}

机构：

[1] Univ Politecn Valencia, Dept Comp Engn, Valencia, Spain

[2] Univ Politecn Cataluna, Dept Arquitectura Comp, Barcelona, Spain

来源：

DESIGN, AUTOMATION & TEST IN EUROPE | 2013年

关键词：

RELIABILITY; DESIGN; DRAM;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Low-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Recent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off. We propose a new fault-tolerant L1 cache, which combines SRAM and eDRAM cells in L1 data caches to provide 100% SRAM hard-error fault coverage. Results show that, compared to a conventional cache and assuming 50% failure probability at low-power mode, leakage and dynamic energy savings are by 85% and 62%, respectively, with a minimal impact on performance.

引用

页码：83 / 88

页数：6