Subthreshold Logic for Low-Area and Energy Efficient True Random Number Generator

被引:0
|
作者
Coustans, Mathieu [1 ]
Cherkaoui, Abdelkarim [2 ]
Fesquet, Laurent [1 ,2 ]
Terrier, Christian [3 ]
Salgado, Stephanie [3 ]
Eberhardt, Thomas [3 ]
Kayal, Maher [1 ]
机构
[1] Swiss Fed Inst Technol EPFL, Lausanne, Switzerland
[2] Univ Grenoble Alpes, CNRS, Grenoble INP, TlMA, F-38000 Grenoble, France
[3] EM Microelect Marin SA, Rue Sors 3, CH-2074 Marin Epagnier, Switzerland
来源
PROCEEDINGS 2018 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS) | 2018年
关键词
Applied Cryptography; Random Numbers Generators; Asynchronous Circuits; Subthreshold Logic;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.
引用
收藏
页数:3
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