Analog/mixed-signal circuit verification using models generated from simulation traces

被引：0

作者：

Little, Scott ^{[1
]}

Walter, David ^{[1
]}

Jones, Kevin ^{[1
]}

Myers, Chris ^{[1
]}

机构：

[1] Univ Utah, Salt Lake City, UT 84112 USA

来源：

AUTOMATED TECHNOLOGY FOR VERIFICATION AND ANALYSIS, PROCEEDINGS | 2007年 / 4762卷

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Formal and semi-formal verification of analog/mixed-signal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the original simulation traces used to generate it plus additional behavior. Information obtained during the model generation process can also be used to refine the simulation and verification process.

引用

页码：114 / +

页数：3

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