共 16 条
- [1] A process variation compensating technique for sub-90nm dynamic circuits 2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, : 205 - 206
- [2] Self-Assembly of Pentacene on Sub-nm Scale Surface Roughness-Controlled Gate Dielectrics Macromolecular Research, 2018, 26 : 942 - 949
- [4] Interferometric Characterisation of Path Length Errors Resulting from Mirror Surface Topography with Sub-nm Reproducibility 9TH LISA SYMPOSIUM, 2013, 467 : 297 - +
- [5] Mask process variation induced OPC accuracy in sub-90nm technology node OPTICAL MICROLITHOGRAPHY XIX, PTS 1-3, 2006, 6154 : U2190 - U2197
- [6] Electronic transport properties of Si thin film from bulk to sub-nm thickness: a first-principles study PHYSICS OF SEMICONDUCTORS, PTS A AND B, 2005, 772 : 83 - 84
- [7] An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations 2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2005, : 221 - 222
- [8] An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 250 - 251