Staircase charge-pumping study of trapping centers at grain-boundary in polysilicon thin film transistors

被引：0
|
作者：
Kim, KJ
Kim, O
机构：
来源：
PROCEEDINGS OF THE THIRD SYMPOSIUM ON THIN FILM TRANSISTOR TECHNOLOGIES | 1997年 / 96卷 / 23期
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D O I：
暂无
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
Polysilicon thin-film transistor (poly-Si TFT) characteristics are evaluated using the staircase charge-pumping (SCP) technique. By measuring the SCP current for various step times, we can obtain the trap state energy distributions at grain-boundaries for different (electron or hole emission) time constant windows. It is confirmed with the SCP technique that a large number of trap states (D-gb greater than or equal to 2x10(11) eV(-1). cm(-2)) exist at the grain-boundary region. As compared to those of n-channel TFT's, the trap states of p-channel TFT's are distributed over the broader time constant range up to 2 ms.
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页码：280 / 288
页数：9
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