Subthreshold Current Reference Suitable For Energy Harvesting: 20ppm/C and 0.1%/V at 140nW

A new CMOS ultra low power, resistor free, current reference is presented which is composed of two current generators, a current scalar, and a current subtraction circuit. Typical reference topologies generally add two current signals with opposing temperature coefficient (TC) polarities to generate a near zero TC reference current (I-r). The proposed circuit generates two currents (I-a and I-b) with the same polarity TCs that are scaled with differing slopes, and subsequently ratioed and subtracted from each other to form an I-r. In each current generator, the amplifier's built-in offset voltages track thermal voltages (V-T) that are forced across resistive MOSFETs, contained in self-cascodes (SC), to make I-a and I-b. The magnitudes of Ia and Ib are adjusted semi independently from their TCs via MOSFET's aspect ratios. Also by setting MOSFET aspect ratios, the current scalar and subtraction circuit deducts the adjusted I-a and I-b from one another to form an Ir optimized for near zero TC. All generated currents are independent of MOSFET's threshold voltage (V-TH) and primarily a function of MOSFET's mobility (u) and thermal voltage (V-T), thus aiding performance to specifications over changes in temperature and fabrication process variations. Simulations, including montecarlo (MC) and worst case (WC), indicates the following specifications are achievable: current consumption (I-dd) similar to 150nA, TC similar to 20 ppm/C, Voltage Coefficient (VC) similar to 0.1 %/V, power supply rejection ratio (PSRR) similar to -65 db, and power-up time (t(su)) similar to 14 milliseconds. Preliminary die size is about 101 micro meter (um) per side.