A new time-multiplexed interconnected architecture with buffering system for multi-chip CNN

The real-time image processing represents one of the application field where the Cellular Neural Networks best show their powerful capabilities because of the full parallel analogue processing feature. On this purpose, the best performances can be carried out with a one-to-one correspondence between the image pixel and the neural cells. Consequently, this leads the need to build very targe CNN chips. In spite of this, these requirements do not agree with the need of the hardware manufacturer to design small chips, more reliable from a VLSI implementation point of view. Among the previously proposed solutions to this leading problem, the authors presented a current-mode interconnection-oriented approach able to carry out wide CNN networks making use of small chips. In this paper a technique to improve the interconnection architecture without any lack of functionality will be presented.