A hierarchical power supply distribution model for full-chip switching noise analysis

被引：1
|
作者：
Chen, HH
机构：
来源：
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 1997年
关键词：
D O I：
10.1109/EPEP.1997.634039
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes the use of a 12x12 SCM power supply distribution model, a 50x50 on-chip power bus model, and a distributed switching circuit model to analyze the on-chip power supply noise for high-performance VLSI design. The integrated model provides a complete analysis of the Vdd distribution, and allows designers to identify the hot spots on the chip and optimize design variables to minimize the noise.
引用
收藏
页码：60 / 63
页数：4
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