Rescuing RRAM-Based Computing From Static and Dynamic Faults

被引:8
|
作者
Lin, Jilan [1 ]
Wen, Cheng-Da [2 ]
Hu, Xing [1 ]
Tang, Tianqi [1 ]
Lin, Ing-Chao [2 ]
Wang, Yu
Xie, Yuan [1 ]
机构
[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA
[2] Natl Cheng Kung Univ, Dept Comp Sci & Informat Engn, Tainan 701, Taiwan
基金
美国国家科学基金会;
关键词
Resistance; Kernel; Fault tolerant systems; Fault tolerance; Reliability; Quantization (signal); Electrodes; Neural network (NN); reliability; resistive random access memory (RRAM); NEURAL-NETWORK; CIRCUIT; ENERGY; RESET;
D O I
10.1109/TCAD.2020.3037316
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Emerging resistive random access memory (RRAM) has shown the great potential of in-memory processing capability, and thus attracts considerable research interests in accelerating memory-intensive applications, such as neural networks (NNs). However, the accuracy of RRAM-based NN computing can degrade significantly, due to the intrinsic statistical variations of the resistance of RRAM cells. In this article, we propose SIGHT, a synergistic algorithm-architecture fault-tolerant framework, to holistically address this issue. Specifically, we consider three major types of faults for RRAM computing: 1) nonlinear resistance distribution; 2) static variation; and 3) dynamic variation. From the algorithm level, we propose a resistance-aware quantization to compel the NN parameters to follow the exact nonlinear resistance distribution as RRAM, and introduce an input regulation technique to compensate for RRAM variations. We also propose a selective weight refreshing scheme to address the dynamic variation issue that occurs at runtime. From the architecture level, we propose a general and low-cost architecture accordingly for supporting our fault-tolerant scheme. Our evaluation demonstrates almost no accuracy loss for our three fault-tolerant algorithms, and the proposed SIGHT architecture incurs performance overhead as little as 7.14%.
引用
收藏
页码:2049 / 2062
页数:14
相关论文
共 50 条
  • [1] RRAM-Based Analog Approximate Computing
    Li, Boxun
    Gu, Peng
    Shan, Yi
    Wang, Yu
    Chen, Yiran
    Yang, Huazhong
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (12) : 1905 - 1917
  • [2] RRAM-based Analog In-Memory Computing
    Chen, Xiaoming
    Song, Tao
    Han, Yinhe
    2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2021,
  • [3] Logic Synthesis for RRAM-Based In-Memory Computing
    Shirinzadeh, Saeideh
    Soeken, Mathias
    Gaillardon, Pierre-Emmanuel
    Drechsler, Rolf
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (07) : 1422 - 1435
  • [4] Reliability Improvement in RRAM-based DNN for Edge Computing
    Oli-Uz-Zaman, Md
    Khan, Saleh Ahmad
    Yuan, Geng
    Wang, Yanzhi
    Liao, Zhiheng
    Fu, Jingyan
    Ding, Caiwen
    Wang, Jinhui
    2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 581 - 585
  • [5] Fault Modeling and Testing of RRAM-based Computing-In Memories
    Yang, Yu Cheng
    Li, Jin-Fu
    2022 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2022), 2022, : 7 - 12
  • [6] A RRAM-based FPGA for Energy-efficient Edge Computing
    Tang, Xifan
    Giacomin, Edouard
    Cadareanu, Patsy
    Gore, Ganesh
    Gaillardon, Pierre-Emmanuel
    PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), 2020,
  • [7] Write or Not: Programming Scheme Optimization for RRAM-based Neuromorphic Computing
    Meng, Ziqi
    Sun, Yanan
    Qian, Weikang
    PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, 2022, : 985 - 990
  • [8] Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing
    Li, Boxun
    Gu, Peng
    Wang, Yu
    Yang, Huazhong
    IEEE DESIGN & TEST, 2016, 33 (01) : 52 - 59
  • [9] PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration
    He, Wangxin
    Meng, Jian
    Gonugondla, Sujan Kumar
    Yu, Shimeng
    Shanbhag, Naresh R.
    Seo, Jae-sun
    2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2023,
  • [10] RRAM-based Reconfigurable In-Memory Computing Architecture with Hybrid Routing
    Zha, Yue
    Li, Jing
    2017 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2017, : 527 - 532