Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

被引：32

作者：

Maheshwaram, Satish ^{[1
]}

Manhas, S. K. ^{[1
]}

Kaushal, Gaurav ^{[1
]}

Anand, Bulusu ^{[1
]}

Singh, Navab ^{[2
]}

机构：

[1] Indian Inst Technol Roorkee, Dept Elect & Comp Engn, Roorkee 247667, Uttar Pradesh, India

[2] ASTAR, Inst Microelect, Singapore 117685, Singapore

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 08期

关键词：

Nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET); power; scaling; vertical complementary metal-oxide-semiconductor (CMOS); MOSFETS;

D O I：

10.1109/LED.2011.2157076

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two-and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.

引用

页码：1011 / 1013

页数：3

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