Lateral NWFET Optimization for Beyond 7nm Nodes

被引：0
|
作者：
Yakimets, D. [1 ,2 ]
Jang, D. [1 ]
Raghavan, P. [1 ]
Eneman, G. [1 ]
Mertens, H. [1 ]
Schuddinck, P. [1 ]
Mallik, A. [1 ]
Bardon, M. Garcia [1 ]
Collaert, N. [1 ]
Mercha, A. [1 ]
Verkest, D. [1 ]
Thean, A. [1 ]
De Meyer, K. [1 ,2 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] Katholieke Univ Leuven, Dept ESAT, Leuven, Belgium
来源：
2015 INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT) | 2015年
关键词：
Lateral gate-all-around FET; nanowire; scaling; design technology co-optimization (DTCO);
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.
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页数：4
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